The present invention relates to a technique which is effectively applicable to the ion implantation technique used in a semiconductor integrated circuit device manufacturing process.
The present invention is further concerned with a semiconductor integrated circuit device which requires a semiconductor region (a doped layer) of a small junction depth, as well as a method for producing the said device, and is particularly concerned with a technique which is effectively applicable to a self-aligned bipolar transistor of high speed and high integration density.
Recently, the application of the ion implantation technique to a semiconductor integrated circuit device using a high energy ion implanter, particularly a monolithic semiconductor integrated circuit device, has been attracting attention of many concerns. In this connection, problems have been pointed out, such as the rise in the temperature of wafer as a work, contamination, and element breakdown caused by charge-up. As examples of literatures describing these problems there are a magazine, "Denshi Zairyo," November 1980 number, pp.63-68 and 130; Japanese Patent Laid Open No.3403/86; a magazine, "Nikkei Microdevices," June 1986 number, pp.50-52; Kenji Gamo, "Handotai Ion Chunyu Gijutsu," Sangyo Tosho K. K. (Jul.31, 1986), pp.204-207; Japanese Patent Laid Open Nos. 17863/89, 162767/89, 28333/84, 10563/89 and 93247/83; and K. Izumi et al., "Nuclear Instruments and Methods in Physics Research," B37/38 North Holland Shuppan (1989), pp.299-303.
Further, as a bipolar transistor manufacturing technique there is known SEPT (Selective Etching of Poly-silicon Technology). According to SEPT, base extraction electrode, emitter opening, emitter region and emitter extraction electrode can be formed by self-alignment with respect to a base region. In a bipolar transistor formed by this technique, therefore, it is not necessary to consider a mask alignment margin in the manufacturing process such as a base-emitter mask alignment margin, so that the area occupied by the bipolar transistor can be reduced. As a result, in a semiconductor integrated circuit device using such bipolar transistors, it is possible to attain a high frequency characteristic and a high integration density. But to this end it is important to reduce the depth of emitter junction.
According to a conventional method commonly used for forming an emitter ]unction in a self-aligned bipolar transistor, an impurity introduced into a polycrystalline silicon film which constitutes an emitter extraction electrode is drive-in diffused in a main surface of a monocrystalline semiconductor substrate to form an emitter region.
A bipolar transistor using a polycrystalline silicon film for each of base and emitter extraction electrodes is also called a double poly-silicon self-aligned bipolar transistor. A bipolar transistor having such a double poly-silicon structure is described, for example, in "Nikkei Microdevices," November 1985 number, pp.67-78.
In addition to the above drive-in diffusion technique, there is also known a preamorphous technique as a technique capable of forming a semiconductor region of a small junction depth. According to this technique, silicon (Si) or germanium (Ge) atoms are implanted in a main surface portion of a semiconductor substrate prior to the implantation of a desired ion which is performed for forming a semiconductor region (a doped layer) on the main surface of the semiconductor substrate, to thereby render the main surface portion amorphous, followed by the implantation of the desired ion, thereby preventing channelling of ions and permitting the formation of a shallow junction.
The above preamorphous technique is described, for example, in an article of Tanaka et al. in "1989, IEEE IEDM, pp.785-788."
In the Tanaka et al.'s article referred to above it is described that in the case where Si atoms are ion-implanted in a monocrystalline semiconductor substrate in advance, unless a heat treatment is performed so that a PN junction is formed in a depth three times as large as the boundary between an amorphous layer and a non-amorphous layer (a monocrystalline region) which are formed on a main surface of the semiconductor substrate, there will remain a crystal defect near the PN junction thus causing a leak current which exerts a bad influence on the device operation.